AD9776 Просмотр технического описания (PDF) - Analog Devices
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AD9776 Datasheet PDF : 56 Pages
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FUNCTIONAL BLOCK DIAGRAM
SYNC_O
SYNC_I
DATACLK_OUT
P1D(15:0)
DELAY
LINE
DELAY
LINE
DATA
ASSEMBLER
I
LATCH
P2D(15:0)
Q
LATCH
CLOCK GENERATION/DISTRIBUTION
2×
2×
2×
n × fDAC/8
n = 0, 1, 2 ... 7
2×
2×
2×
DIGITAL CONTROLLER
SERIAL
PERIPHERAL
INTERFACE
POWER-ON
RESET
Figure 2. Functional Block Diagram
AD9776/AD9778/AD9779
CLOCK
MULTIPLIER
2×/4×/8×
SYNC1
16-BIT
IDAC
CLK+
CLK–
IOUT1_P
IOUT1_N
SYNC1
10
GAIN
10
GAIN
10
GAIN
10
GAIN
16-BIT
QDAC
IOUT2_P
IOUT2_N
VREF
I120
AUX1_P
AUX1_N
AUX2_P
AUX2_N
Rev. A | Page 3 of 56
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