18+1 Channel Voltage Buffers for TFT LCD
OUTLINE DIMENSIONS (Dimensions shown in millimeters)
H: Exposed pad (3.05x3.05 mm)
EC5579
DIMN
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
Q
MM
MIN
NOM
MAX
—
—
1.20
0.05
—
0.15
0.95
1.00
1.05
0.17
0.20
0.23
0.09
—
0.16
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
0.45
0.60
0.75
1.00(REF)
0˚
3.5˚
7˚
THERNALLY ENHANCED DINENSIONS (SHOW IN WW)
PAD SIZE
E2
D2
MIN.
MAX.
MIN.
MAX.
160X16E 3.05
4.06
3.05
4.06
NOTE
1. JEDEC OUTLINE:
NS-026 ABC
NS-026 ABC-HD (THERNALLY ENHANCED VARIATIONS ONLY)
2. DATUN PLANE H IS LOCATED AT THE BOTTOM OF THE MOLE
PATTING LINE COINCIDENT WITH WHERE THE LEAD EXITS THE
BODY.
3. DIMENSIONS D1 AND E1 DO NOR INCLUDE MOLD
PROTRUSION.ALLOWABLE PROTRUSION IS 0.25mm PER
SIDE.DIMENSICNS D1 AND E1 DO INCLUDE MOLD MISWATCH
AND ARE DETERMINED AT DATUN PLANE H
4.DINENSION b DOES NOT INCLUDE DANBAR PROTRUSION.
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 12
2007/06/29