MT46V16M8TG-8 Просмотр технического описания (PDF) - Micron Technology
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MT46V16M8TG-8 Datasheet PDF : 68 Pages
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PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
CAPACITANCE (x4, x8)
(Note: 13; notes appear on pages 50–53)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL MIN
DCIO
–
DCI1
–
DCI2
–
CIO
4.0
CI1
2.0
CI2
2.0
CI3
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
MAX
PARAMETER/CONDITION
SYMBOL -75/-75Z -8
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); IDD0
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
105 100
cyle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
IDD1
120 110
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDD2P
3
3
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); IDD2F
45
35
CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
18
18
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
IDD3N
45
35
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R
110
90
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank IDD4W 110 90
active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
IDD5
tRC = 15.625µs
IDD6
220 205
5
5
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
IDD7
2
3
Low power (L)
IDD7
1
1
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
IDD8
auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
325 260
UNITS
mA
NOTES
22, 48
mA 22,48
mA 23, 32, 50
mA
51
mA 23, 32, 50
mA
47
mA 22, 48
mA
22
mA 22, 50
mA 27, 50
mA
11
mA
11
mA 22,49
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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