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DSP56852 Просмотр технического описания (PDF) - Freescale Semiconductor

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DSP56852
Freescale
Freescale Semiconductor 
DSP56852 Datasheet PDF : 48 Pages
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SS
(Input)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
SS is held High on master
tC
tR
tCL
tCH
tF
tCL
tDH
tDS
tCH
MSB in
tDI
tCH
Bits 14–1
tDV
tF
tR
LSB in
tDI(ref)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 4-17 SPI Master Timing (CPHA = 0)
SS
(Input)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
tDV(ref)
SS is held High on master
tC
tF
tCL
tCH
tCL
tCH
MSB in
tDI
tR
Bits 14–1
tDV
tR
tF
tDS
tDH
LSB in
MOSI
(Output)
Master MSB out
tF
Bits 14– 1
Master LSB out
tR
Figure 4-18 SPI Master Timing (CPHA = 1)
56852 Technical Data, Rev. 8
30
Freescale Semiconductor

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