NXP Semiconductors
74AHC126; 74AHCT126
Quad buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74AHC126
74AHCT126
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
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Fig 4. Pin configuration SO14 and TSSOP14
74AHC126
74AHCT126
terminal 1
index area
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND(1)
13 4OE
12 4A
11 4Y
10 3OE
9 3A
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Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
output enable input 1 (active HIGH)
data input 1
data output 1
output enable input 2 (active HIGH)
data input 2
data output 2
ground (0 V)
data output 3
data input 3
output enable input 3 (active HIGH)
data output 4
data input 4
output enable input 4 (active HIGH)
supply voltage
74AHC_AHCT126_4
Product data sheet
Rev. 04 — 12 August 2009
© NXP B.V. 2009. All rights reserved.
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