74LVC1G10 Просмотр технического описания (PDF) - NXP Semiconductors.
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74LVC1G10 Datasheet PDF : 14 Pages
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NXP Semiconductors
74LVC1G10
Single 3-input NAND gate
6. Pinning information
6.1 Pinning
74LVC1G10
A1
6C
GND 2
5 VCC
B3
4Y
001aag689
Fig 4. Pin configuration SOT363
and SOT457
74LVC1G10
A1
6C
GND 2
5 VCC
B3
4Y
001aag690
Transparent top view
Fig 5. Pin configuration SOT886
6.2 Pin description
Table 3.
Symbol
A
GND
B
Y
VCC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4. Function table[1]
Input
A
B
C
H
H
H
L
X
X
X
L
X
X
X
L
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74LVC1G10
A1
6C
GND 2
5 VCC
B3
4Y
001aag691
Transparent top view
Fig 6. Pin configuration SOT891
Output
Y
L
H
H
H
74LVC1G10_1
Product data sheet
Rev. 01 — 2 October 2007
© NXP B.V. 2007. All rights reserved.
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