Philips Semiconductors
Quad 2-input NAND gate (open drain)
AC WAVEFORMS
Product specification
74LVC38A
handbook, full pagewidth
VI
nA, nB input
GND
VCC
nY output
VOL(2)
VM (1)
t PLZ
VX (3)
t PZL
VM (1)
MNA700
(1) VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5VCC at VCC < 2.7 V.
(2) VOL and VOH are typical output voltage drop that occur with the output load.
(3) VX = VOL + 0.3 V at VCC ≥ 2.7 V.
VX = VOL + 0.15 V at VCC < 2.7 V.
Fig.6 The input nA, nB to output nY propagation delays.
handbook, full pagewidth
VCC
VI
PULSE
GENERATOR
VO
D.U.T.
RT
VEXT
RL
CL
RL
MNA616
VCC
1.2
2.7
3.3 to 3.6
VEXT
2 × VCC
6V
6V
VI
VCC
2.7 V
2.7 V
CL
30 pF
50 pF
50 pF
Note
1. The circuit performs better when RL = 1000 Ω.
RL
500 Ω(1)
500 Ω
500 Ω
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
tr = tf ≤ 2.5 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.7 Load circuitry for switching times.
2004 Mar 22
8