GM72V66841CLT Просмотр технического описания (PDF) - LG

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GM72V66841CLT

2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM

LG 

LG Semicon

Mode Register Configuration

The mode register is set by the input to the

address pins (A0 to A13) during mode register

set cycles. The mode register consists of five

sections, each of which is assigned to address

pins.

A13, A12, A11, A10, A9, A8: (OPCODE):

The synchronous DRAM has two types of write

modes. One is the burst write mode, and the

other is the single write mode. These bits specify

write mode.

Burst read and BURST WRITE:

Burst write is performed for the specified burst

length starting from the column address specified

in the write cycle.

GM72V66841CT/CLT

Burst read and SINGLE WRITE:

Data is only written to the column address

specified during the write cycle, regardless of the

burst length.

A7:

Keep this bit Low at the mode register set cycle.

A6, A5, A4: (LMODE):

These pins specify the CAS latency.

A3: (BT):

A burst type is specified . When full-page burst is

performed, only "sequential" can be selected.

A2, A1, A0: (BL):

These pins specify the burst length.

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

OPCODE

0

LMODE BT

BL

A6 A5 A4 CAS Latency

000

R

A3 Burst Type

0 Sequential

Burst Length

A2 A1 A0

BT=0 BT=1

001

R

1 Interleave

000 1 1

010

2

001 2 2

011

3

010 4 4

1 XX

R

011 8 8

100 R R

101 R R

A13 A12 A11 A10 A9 A8

Write mode

110 R R

0 0 0 0 0 0 Burst read and BURST WRITE

1 1 1 F.P. R

XXXX 0 1

R

X X X X 1 0 Burst read and SINGLE WRITE

XXXX 1 1

R

F.P. = Full Page

(512:GM72V66841CT/CLT)

R is Reserved (inhibit)

X: 0 or 1

15

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