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290479-004

PCI, CACHE AND MEMORY CONTROLLER PCMC

Intel 

82434LX 82434NX

Signal

M IO

DC

WR

Type

Description

in BUS CYCLE DEFINITION (MEMORY INPUT-OUTPUT DATA CONTROL WRITE

READ) M IO D C and W R define Host Bus cycles as shown in the table below

M IO

Low

Low

Low

Low

High

High

High

High

DC

Low

Low

High

High

Low

Low

High

High

WR

Low

High

Low

High

Low

High

Low

High

Bus Cycle Type

Interrupt Acknowledge

Special Cycle

I O Read

I O Write

Code Read

Reserved

Memory Read

Memory Write

HLOCK

CACHE

KEN

Interrupt acknowledge cycles are forwarded to the PCI Bus as PCI interrupt

acknowledge cycles (i e C BE 3 0 e 0000 during the address phase) All I O cycles

and any memory cycles that are not directed to memory controlled by the PCMC DRAM

controller are forwarded to PCI The Pentium processor generates six different types of

special cycles The special cycle type is encoded on the BE 7 0 lines

in HOST BUS LOCK The Pentium processor asserts HLOCK to indicate the current bus

cycle is locked HLOCK is asserted in the first clock of the first locked bus cycle and is

negated after the BRDY is returned for the last locked bus cycle The Pentium

processor guarantees HLOCK to be negated for at least one clock between back-to-

back locked operations When a CPU locked cycle is directed to main memory the

PCMC guarantees that once the locked operation begins in main memory the CPU has

exclusive access to main memory (i e PCI master accesses to main memory will not be

initiated until the CPU locked operation completes) When a CPU locked cycle is

directed to PCI the PCMC arbitrates for PLOCK (PCI LOCK ) before initiating the

cycle on PCI except when the cycle is to the memory range defined by the Frame

Buffer Range Register and the No Lock Requests bit in that register is set to 1

in CACHEABILITY The Pentium processor asserts CACHE to indicate the internal

cacheability of a read cycle or that a write cycle is a burst write-back cycle If the CPU

drives CACHE inactive during a read cycle the returned data is not cached

regardless of the state of KEN The CPU asserts CACHE for cacheable data reads

cacheable code fetches and cache line write-backs CACHE is driven along with the

cycle definition pins

out CACHE ENABLE The PCMC asserts KEN to indicate to the CPU that the current

cycle is cacheable KEN is asserted for all accesses to memory ranges 0 – 512-KBytes

and 1024-KBytes to the top of main memory controlled by the PCMC when the Primary

Cache Enable bit is set to 1 except in the following case KEN is not asserted for

accesses to the top 64-KByte of main memory controlled by the PCMC when the

SMRAM Enable bit in the DRAM Control Register (Offset 57h) is set to 1 and the area is

not write protected If the area is write protected and cacheable KEN is asserted for

code read cycles but is not asserted during data read cycle KEN is asserted for any

CPU access within the range of 512-KBytes – 1024-KBytes if the corresponding Cache

Enable bit in the PAM 6 0 Registers (offsets 59h – 5Fh) is set to 1 When the Pentium

processor indicates that the current read cycle can be cached by asserting CACHE

and the PCMC responds with KEN the cycle is converted into a burst cache line fill

The CPU samples KEN with the first of either BRDY or NA

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