A8513KLYTR-T Просмотр технического описания (PDF) - Allegro MicroSystems

Номер в каталоге

Компоненты Описание

производитель

A8513KLYTR-T

Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver

Allegro MicroSystems 

A8513

Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

Pin-out Diagram

NC 1

NC 2

SW 3

OVP 4

VIN 5

FAULT 6

VDD 7

NC 8

PAD

16 NC

15 COMP

14 GND

13 GND

12 ISET

11 EN/PWM

10 LED

9 NC

SW 1

OVP 2

VIN 3

FAULT 4

VDD 5

PAD

10 COMP

9 GND

8 ISET

7 EN/PWM

6 LED

LP Package

LY Package

Terminal List Table

Name

Number

LP

LY

COMP

15

10

¯F¯ ¯A ¯¯U ¯¯L¯ ¯T¯

6

4

GND

13,14

9

ISET

12

8

LED

10

6

NC

1,2,8,9,16

–

OVP

4

2

PAD

–

–

EN/PWM

11

7

SW

3

1

VDD

7

5

VIN

5

3

Function

Output of the error amplifier and compensation node. Connect compensation network from

this pin to GND for control loop compensation.

This pin is used to indicate fault conditions. Logic low indicates that the A8513 has

a fault present.

Ground.

Connect the RISET resistor between this pin and GND to set the 100% LED current level.

Connect the cathode of the LED string to this pin.

No connection.

This pin is used to sense an overvoltage condition. Connect a resistive divider from the

VOUT node to this pin to adjust the Overvoltage Protection (OVP).

Exposed pad of the package providing enhanced thermal dissipation. This pad must be

connected to the ground plane(s) of the PCB with at least 8 thermal vias, directly in the pad.

PWM dimming pin. Used to control LED intensity by using pulse width modulation.

The drain of the internal NMOS switch of the boost converter.

Output of internal LDO. Connect a 0.1 μF decoupling capacitor between this pin and GND.

Input power to the A8513.

Thermal Characteristics*may require derating at maximum conditions, see application information

Characteristic

Symbol

Test Conditions*

Package Thermal Resistance

(Junction to Ambient)

RθJA

On 4-layer PCB based on JEDEC standard

LP package

On 2-layer PCB with 3.8 in.2 of copper area each side

On 4-layer PCB based on JEDEC standard

LY package

On 2-layer PCB with 2.5 in.2 of copper area each side

Package Thermal Resistance

(Junction to Pad)

RθJP

*To be verified by characterization. Additional thermal information available on the Allegro® website.

Value Unit

34 ºC/W

43 ºC/W

48 ºC/W

48 ºC/W

2 ºC/W

Allegro MicroSystems, Inc.

3

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Share Link: