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AAT4292

Seven Channel High-Side I/O Expander

Analog Technology Inc 

SmartSwitchTM

age. When the device is switched ON, the gate voltage

is quickly increased to the threshold level of the MOSFET.

Once at this level, the current begins to slew as the gate

voltage is slowly increased until the MOSFET becomes

fully enhanced. Once it has reached this point, the gate

is quickly increased to the full input voltage and RDS(ON) is

minimized.

The ON/OFF states of the seven MOSFET switches are

controlled by the EN/SET serial clock input. An internal

control counter is clocked on the rising edges of the EN/

SET pin and is decoded into 128 possible states of the

MOSFET (see Table 1 and Table 2). The counter can be

clocked at speeds up to 1MHz, but the count value is not

latched until clocking has stopped and the EN/SET pin

has remained high for the tLAT timeout (approximate

1.15μs typical). The first rising edge of EN/SET enables

the AAT4292 and is counted as the first clock.

There are four address switch bank in AAT4292, which is

selected by the corresponding rising edges 33 to 36,

after remaining the EN/SET high for the tLAT timeout,

then the clock number is latched and the relevant

address switch bank (0 to 3) is asserted. Next, the cor-

responding rising edges of Data from 1 to 32 can be

serial submitted, and closed by the EN/SET remaining

high for tLAT timeout. After the timeout tLAT, the outputs

status is updated accordingly.

The AAT4292 is disabled after the EN/SET pin has tran-

sitioned and remained in a logic low for tOFF timeout, and

the quiescent current drops to 0.1μA typically.

PRODUCT DATASHEET

AAT4292

Seven Channel High-Side I/O Expander

AS2Cwire Serial Interface

The ON/OFF states of the seven output channels are con-

trolled by the EN/SET serial data input. An internal con-

trol counter is clocked on the rising edge of the EN/SET

pin and is decoded into one of 128 possible states using

a short address and data word (see Tables 1 and 2).

AS2Cwire relies on the number of rising edges of the EN/

SET pin to address and load the registers, as illustrated

in Figure 1. AS2Cwire latches data (1 to 32 edges) or

address (33 to 36 edges) after the EN/SET pin has been

held high for time tLAT. The interface records rising edges

of the EN/SET pin and decodes them into one of four

addresses corresponding to the address table (Table 1),

or 1 of 32 data settings corresponding to the switch code

table (Table 2). The combined address and data is used

to decode one of 128 possible switch states. Address and

Data are differentiated by the number of rising edges on

the EN/SET pin. 1 to 32 rising edges signifies Data, and

33 to 36 rising edges signifies Address. The counter can

be clocked at speeds up to 1MHz, such that intermediate

states are not visible. The first rising edge of EN/SET

enables the IC and turns the switches OUT3-OUT7 on.

Once the final clock cycle is received, the EN/SET pin is

held high to maintain the device setting. The device is

disabled after the EN/SET pin transitions to a logic low

state for tOFF timeout (approximate 1.3μs typical).

Address Code

Address Switch

Bank Code

0

1

2

3

EN/SET

Rising Edges

33

34

35

36

Table 1: AS2Cwire Address Table.

4292.2008.08.1.0

www.analogictech.com

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