AD1836 Просмотр технического описания (PDF) - Analog Devices
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производитель
AD1836 Datasheet PDF : 18 Pages
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PRELIMINARY TECHNICAL DATA
DIGITAL FILTERS at 44.1 kHz
ADC DECIMATION FILTER
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
Min
Typ
Max
20
± 0.0001
22
24
120
TBD
20
± 0.01
22
24
70
TBD
AD1836
Unit
kHz
dB
kHz
kHz
dB
µs
kHz
dB
kHz
kHz
dB
µs
TIMING
Parameter
MASTER CLOCK AND RESET
tMH
MCLK High
tML
tMCLK
fMCLK
tPDR
MCLK Low
MCLK Period
MCLK Freq
PD/RST Low
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCODE
tCOD
tCOH
tCOTS
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Hold
COUT Three-State
DAC SERIAL PORT
Normal Modes
tDBH
DBCLK High
tDBL
DBCLK Low
tDBP
DBCLK Period
fDB
DBCLK Freq
tDLS
DLRCLK Setup
tDLH
DLRCLK Hold
tDDS
DSDATA Setup
tDDH
DSDATA Hold
Packed 128, 256 Modes
tDBH
tDBL
tDBP
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
DBCLK Period
DBCLK Freq
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
REV. PrC
Min
Max
min
max
min
max
min
max
min
max
4500
min
min
min
min
min
min
min
max
max
min
max
min
min
min
max
min
min
min
min
min
min
min
max
min
min
min
min
–3–
Unit
Comments
ns
ns
ns
ns
MCLK Periods
256 × fS
512 × fS
768 × fS
Reset to SPI Register Write
ns
ns
ns
ns
To CCLK Rising
ns
From CCLK Rising
ns
To CCLK Rising
ns
From CCLK Falling
ns
From CCLK Falling
ns
From CCLK Falling
ns
From CCLK Falling
ns
From CCLK Falling
ns
ns
ns
ns
ns
To DBCLK Rising
ns
From DBCLK Rising
ns
To DBCLK Rising
ns
From DBCLK Rising
ns
ns
ns
ns
ns
To DBCLK Rising
ns
From DBCLK Rising
ns
To DBCLK Rising
ns
From DBCLK Rising
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