AD1888 Просмотр технического описания (PDF) - Analog Devices

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AD1888

AC ’97 SoundMAX® Codec

Analog Devices 

AD1888

General-Purpose Register (Index 20h)

Reg

No. Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

20h General-Purpose X

X X X DRSS1 DRSS0 X MS LPBK X X X

XX X

X 0000h

This register should be read before writing to generate a mask only for the bit(s) that need to be changed. All registers not shown and bits containing an X are

assumed to be reserved.

LPBK

MS

DRSS [1:0]

Loopback Control. This bit enables the digital internal loopback from the ADC to the front DAC. This feature is

normally used for test and troubleshooting.

0 = No Loopback (Default)

1 = Loopback PCM digital data from ADC output to DAC

See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center/LFE DACs.

MIC Select. Selects Mono MIC input.

0 = Select MIC1, from rear panel MIC jack

1 = Select MIC2, from front panel MIC jack

Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R

(n + 1) data are by default provided in output slots 10 and 11.

00: PCM L, R n + 1 Data is on Slots 10, 11 (reset default)

01: PCM L, R n + 1 Data is on Slots 7, 8

10: Reserved

11: Reserved

Audio Interrupt and Paging Mechanism Register (Index 24h)

Reg

No. Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

24h Audio Interrupt

I4

and Paging

X

X X I0 X

X X X X X X PG3 PG2 PG1 PG0 xxxxh

This register controls the audio interrupt and paging mechanism. All registers not shown and bits containing an X are assumed to be reserved.

PG[3:0]

I0

I4

Page Selector (Read Only). This register is used to describe page selector capability for extended features.

Reading these bits returns 0h, which describes page selection as vendor specific only.

INTERRUPT ENABLE (R/W). This enables interrupt generation.

0 = Interrupt Generation is Masked (Default)

1 = Interrupt Generation is Unmasked

The S/W should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with

modem slot 12 GPI functionality.

AC ’97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, S/W could

poll the interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an inter-

rupting event has occurred.

INTERRUPT STATUS (R/W). This bit provides interrupt status and clear capability.

0 = Interrupt is Clear

1 = Interrupt was Generated

Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt

enable (I0) status. An interrupt in the GPI in slot 12 in the ac link will follow this bit change when interrupt enable

(I0) is unmasked.

–16–

REV. 0

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