AD5543 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD5543

Current Output/Serial Input, 16-/14-Bit DACs

Analog Devices 

AD5543/AD5553

Data Sheet

Parameter

AC CHARACTERISTICS4

Output Voltage Settling Time

Reference Multiplying Bandwidth (BW)

DAC Glitch Impulse

Feedthrough Error

Digital Feedthrough

Total Harmonic Distortion

Output Spot Noise Voltage

Symbol

tS

BW

Q

VOUT/VREF

Q

THD

eN

Test Conditions/Comments

To ±0.1% of full scale,

Data = 0x0000 to 0xFFFF to 0x0000 for AD5543

Data = 0x0000 to 0x3FFF to 0x0000 for AD5553

VREF = 100 mV rms, data = 0xFFFF

VREF = 0 V, data = 0x7FFF to 0x8000 for AD5543

Data = 0x0000, VREF = 100 mV rms, same channel

CS = 1 and fCLK = 1 MHz

VREF = 5 V p-p, data = 0xFFFF, f = 1 kHz

f = 1 kHz, BW = 1 Hz

5 V ± 10% Unit

0.5

µs typ

6.6

7

−83

7

−103

12

MHz typ

nV-sec

dB

nV-sec

dB typ

nV/√Hz

1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is

tied to the amplifier output. The +IN operational amplifier is grounded, and the DAC IOUT is tied to the −IN operational amplifier. Typical values represent average

readings measured at 25°C.

2 These parameters are guaranteed by design and are not subject to production testing.

3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.

4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

TIMING DIAGRAMS

SDI

D15 D14 D13 D12 D11 D10 D9

D8

D1 D0

CLK

tCSS

tDS

tDH

tCH

tCL

CS

Figure 4. AD5543 Timing Diagram

SDI

D13 D12 D11 D10 D9

D8

D7

D6

tCSH

D1 D0

CLK

tCSS

tDS

tDH

tCH

tCL

tCSH

CS

Figure 5. AD5553 Timing Diagram

Rev. G | Page 4 of 20

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