AD7765BRUZ Просмотр технического описания (PDF) - Analog Devices

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AD7765BRUZ

24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface

Analog Devices 

Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameters

AVDD1 to Ground

AVDD2, AVDD3, AVDD4 to Ground

DVDD to Ground

VINA+, VINA− to Ground1

VIN+, VIN− to Ground1

Digital Input Voltage to Ground2

VREF+ to Ground3

Input Current to Any Pin Except Supplies4

Operating Temperature Range, Commercial

Storage Temperature Range

Junction Temperature

θJA Thermal Impedance (1s0p)5

θJA Thermal Impedance (2s2p)6, 7

θJC8 Thermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

ESD

Rating

−0.3 V to +2.8 V

−0.3 V to +6 V

−0.3 V to +2.8 V

−0.3 V to +6 V

−0.3 V to +6 V

−0.3 V to +2.8 V

−0.3 V to +6 V

±10 mA

−40°C to +85°C

−65°C to +150°C

150°C

143°C/W

71.1°C/W

20°C/W

215°C

220°C

1 kV

1 The absolute maximum voltage for VIN−, VIN+, VINA−, and VINA+ is 6.0 V or

AVDD3 + 0.3 V, whichever is lower.

2 The absolute maximum voltage on the digital input is 3.0 V or DVDD + 0.3 V,

whichever is lower.

3 The absolute maximum voltage on the VREF+ input is 6.0 V or AVDD4 + 0.3 V,

whichever is lower.

4 Transient currents of up to 100 mA do not cause SCR latch-up.

5 1s0p means a single-layer printed circuit board (PCB), which includes

one signal layer and zero power layers.

6 2s2p means a 4-layer PCB, which includes two signal layers and two power layers.

7 θJA for a 2s2p PCB is derived from simulation.

8 The revised θJC (thermal impedance) is derived from simulation.

AD7765

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. C | Page 9 of 33

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