AD7960BCPZ-RL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD7960BCPZ-RL7 Datasheet PDF : 24 Pages
| |||
Data Sheet
AD7960
Parameter
Test Conditions/Comments Min
Typ
Max
Unit
Converting: Internal Reference Buffer
Disabled
Echoed clock mode, CNV± in
LVDS mode
46.5
56.2
mW
Converting: Internal Reference Buffer
Enabled
Echoed clock mode, CNV± in
LVDS mode
64.5
76.4
mW
Converting: Internal Reference Buffer
Disabled
Self clocked mode, CNV± in
CMOS mode7
39
47.4
mW
Power-Down
EN3 to EN0 = X000
7.2
94.5
µW
Energy per Conversion
Self clocked, CNV± in CMOS
mode7
7.8
9.5
nJ/sample
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+85
°C
1 The minimum and maximum values are guaranteed by characterization.
2 Using an external reference.
3 See Table 8 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or
lower.
4 The REFIN pin is tied to 0 V in this mode.
5 The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV.
6 The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed.
7 CNV+ works as a CMOS input when CNV− is grounded. See Table 6 for additional information.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions
Acquisition Time
CNV± High Time
CNV± to D± (MSB) Ready
CNV± to Last CLK± (LSB) Delay
CLK± Period1
CLK± Frequency
CLK± to DCO± Delay (Echoed Clock Mode)
DCO± to D± Delay (Echoed Clock Mode)
CLK± to D± Delay
Symbol
tCYC
tACQ
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
tCLKD
Min
Typ
Max
200
tCYC − 100
10
0.6 × tCYC
200
160
3.33
4
(tCYC − tMSB + tCLKL)/n
250
300
0
3
5
0
1
0
3
5
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
1 For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read, giving the maximum CLK±
frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 18; in self clocked interface mode, n = 20.
Rev. 0 | Page 5 of 24
Share Link: 