ADMC401 Просмотр технического описания (PDF) - Analog Devices

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производитель

ADMC401

Single-Chip, DSP-Based High Performance Motor Controller

Analog Devices 

ADMC401

Parameter

Min

Max

Unit

Bus Request/Grant

Timing Requirements:

tBH

BR Hold after CLKOUT High1

tBS

BR Setup before CLKOUT Low1

Switching Characteristics:

tSD

tSDB

tSE

tSEC

tSDBH

tSEH

CLKOUT High to DMS, PMS, BMS,

RD, WR Disable

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS, BMS,

RD, WR Enable

DMS, PMS, BMS, RD, WR

Enable to CLKOUT High

DMS, PMS, BMS, RD, WR

Disable to BGH Low2

BGH High to DMS, PMS, BMS,

RD, WR Enable2

0.25tCK +2

0.25tCK + 17

0

0

0.25tCK – 7

0

0

ns

ns

0.25tCK + 10

ns

ns

ns

ns

ns

ns

NOTES

1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized

on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.

2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

BR

CLKOUT

PMS, DMS

BMS, RD

WR

BG

BGH

t BH

t BS

t SD

t SEC

t SDB

t SE

t SDBH

t SEH

Figure 3. Bus Request–Bus Grant

REV. B

–7–

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