ADN2812 Просмотр технического описания (PDF) - Analog Devices

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ADN2812

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

Data Sheet

ADN2812

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance, especially on Pin 23, which is the ground return

for the output buffers. The exposed pad should be connected

to the GND plane using plugged vias so that solder does not

leak through the vias during reflow.

Use of a 10 µF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they

should be placed between the IC power supply VCC and VEE

and as close as possible to the ADN2812 VCC pins.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series induc-

tance, especially on Pin 24, which supplies power to the high

speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN

output buffers. Refer to the schematic in Figure 24 for recom-

mended connections.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

Cplane = 0.88ε r A/d (pF)

where:

εr is the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm2).

d is the separation between planes (mm).

For FR-4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2.

VCC

+

10µF

VCC

100Ω × 4

0.1µF 1nF

50Ω

TRANSMISSION LINES

DATAOUTP

DATAOUTN

CLKOUTP

CLKOUTN

VCC

0.1µF

1nF

0.1µF

50Ω

TIA 50Ω

CIN

CIN

VCC

VCC

VREF

NIN

PIN

SLICEP

SLICEN

VEE

32 31 30 29 28 27 26

1

2

3

EXPOSED PAD

4

TIED OFF TO

5

VEE PLANE

WITH VIAS

6

7

8

9 10 11 12 13 14 15

25

24

23

22

21

20

19

18

17

16

VCC

VEE

LOS

SDA

SCK

SADDR5

VCC

VEE

1nF 0.1µF

VCC

µC

I2C

CONTROLLER

1nF 0.1µF

VCC

RTH

VCC

0.1µF

NC

1nF

µC

0.47µF ± 20% >300MΩ

INSULATION RESISTANCE

NC = NO CONNECT

Figure 24. Typical Applications Circuit

Rev. E | Page 21 of 28

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