ADN2815(Rev0) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADN2815
(Rev.:Rev0)

Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC

Analog Devices 

VCC

TIA

ADN2815

V1 CIN V2 PIN

+

50Ω

V1b CIN V2b

VREF BUFFER

50Ω

–

NIN

CDR

COUT

COUT

DATAOUTP

DATAOUTN

ADN2815

1

2

V1

V1b

V2

V2b

3

4

VREF

VDIFF

VTH

VDIFF = V2–V2b

VTH = ADN2815 QUANTIZER THRESHOLD

NOTES:

1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.

2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE

VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.

3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO

THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,

EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER

DOES NOT RECOGNIZE THIS AS A VALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2815. THE

QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.

Figure 21. Example of Baseline Wander

Rev. 0 | Page 21 of 24

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