ADV7330 Просмотр технического описания (PDF) - Analog Devices
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ADV7330 Datasheet PDF : 76 Pages
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ADV7330
HSYNC_I/P
VSYNC_I/P
A
BLANK_I/P
Y7–Y0
Cb Y Cr Y
B
A = 32 CLK CYCLES FOR 525p
A = 24 CLK CYCLES FOR 626p
AS RECOMMENDED BY STANDARD
B (MIN) = 244 CLK CYCLES FOR 525p
B (MIN) = 264 CLK CYCLES FOR 625p
Figure 9. PS 4:2:2, 1 × 8-Bit Interleaved Input Timing Diagram
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
Y7–Y0
Cb Y Cr Y
*SELECTED BY ADDRESS 44h BIT 7
PAL = 264 CLK CYCLES
NTSC = 244 CLK CYCLES
Figure 10. SD Timing Input for Timing Mode 1
t3
SDA
t5
t3
SCLK
t6
t1
t2
t7
t4
t8
Figure 11. MPU Port Timing Diagram
–10–
REV. B
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