ADV7393 Просмотр технического описания (PDF) - Analog Devices

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ADV7393

Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Analog Devices 

ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

GND_IO

VDD_IO

8-BIT SD

OR

8-BIT ED/HD

DGND (2)

FUNCTIONAL BLOCK DIAGRAMS

VDD (2)

SCL SDA ALSB

SFL

AGND VAA

VBI DATA SERVICE

INSERTION

SDR/DDR

SD/ED/HD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

ASYNC

BYPASS

YCrCb

HDTV

TEST

PATTERN

GENERATOR

MPU PORT

SUBCARRIER FREQUENCY

LOCK (SFL)

ADV7390/ADV7391

11-BIT

DAC 1

ADD

SYNC

PROGRAMMABLE

LUMINANCE

FILTER

YCrCb

TO

RGB

16×

FILTER

11-BIT

DAC 2

ADD

BURST

PROGRAMMABLE

CHROMINANCE

FILTER

SIN/COS DDS

BLOCK

16×

FILTER

11-BIT

DAC 3

PROGRAMMABLE

ED/HD FILTERS

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

YCbCr

TO

RGB MATRIX

4×

FILTER

POWER

MANAGEMENT

CONTROL

VIDEO TIMING GENERATOR

16×/4× OVERSAMPLING PLL

REFERENCE

AND CABLE

DETECT

DAC 1

DAC 2

DAC 3

RSET

RESET

HSYNC

VSYNC

CLKIN PVDD PGND EXT_LF

Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)

COMP

GND_IO

VDD_IO

8-BIT SD

DGND (2)

VDD (2)

SCL SDA ALSB

SFL

AGND VAA

VBI DATA SERVICE

INSERTION

SDR/DDR

SD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

MPU PORT

SUBCARRIER FREQUENCY

LOCK (SFL)

ADV7390BCBZ

ADD

SYNC

PROGRAMMABLE

LUMINANCE

FILTER

16×

FILTER

11-BIT

DAC 1

ADD

BURST

PROGRAMMABLE

CHROMINANCE

FILTER

SIN/COS DDS

BLOCK

16×

FILTER

DAC 1

POWER

MANAGEMENT

CONTROL

VIDEO TIMING GENERATOR

16× OVERSAMPLING PLL

REFERENCE

AND CABLE

DETECT

RSET

RESET

HSYNC

VSYNC

CLKIN PVDD PGND EXT_LF

Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)

COMP

GND_IO

VDD_IO

8-/10-/16-BIT SD

OR

8-/10-/16-BIT ED/HD

DGND (2)

VDD (2)

VBI DATA SERVICE

INSERTION

SDR/DDR

SD/ED/HD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

RGB

TO

YCrCb

MATRIX

ASYNC

BYPASS

YCrCb

HDTV

TEST

PATTERN

GENERATOR

SCL SDA ALSB

SFL

AGND VAA

MPU PORT

ADV7392/ADV7393

SUBCARRIER FREQUENCY

LOCK (SFL)

12-BIT

DAC 1

ADD

SYNC

PROGRAMMABLE

LUMINANCE

FILTER

YCrCb

TO

RGB

16×

FILTER

12-BIT

DAC 2

ADD

BURST

PROGRAMMABLE

CHROMINANCE

FILTER

SIN/COS DDS

BLOCK

16×

FILTER

12-BIT

DAC 3

PROGRAMMABLE

ED/HD FILTERS

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

YCbCr

TO

RGB MATRIX

4×

FILTER

POWER

MANAGEMENT

CONTROL

VIDEO TIMING GENERATOR

16x/4x OVERSAMPLING PLL

REFERENCE

AND CABLE

DETECT

DAC 1

DAC 2

DAC 3

RSET

RESET

HSYNC

VSYNC

CLKIN PVDD PGND EXT_LF

Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)

COMP

Rev. G | Page 6 of 108

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