AIC811-46PV Просмотр технического описания (PDF) - Analog Intergrations

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AIC811-46PV

Reset Circuits with Manual Reset Input

Analog Intergrations 

BLOCK DIAGRAM

VCC

GND

R1

Bandgap

-

Reset Generator

+

R2

AIC811/AIC812

RESET

(RESET)

RPULL_UP

20K

MR

PIN DESCRIPTIONS

GND Pin

: Ground.

RESET Pin (AIC811) : Active low output pin. RESET Output remains low while Vcc below reset

threshold.

RESET Pin (AIC812) : Active high output pin. RESET output remains high while Vcc below reset

threshold.

MR Pin

: Logic low manual reset input. This active-low input has an internal 20kΩ pull-up

resistor. It can be driven by a TTL or CMOS, or shorted to ground with a switch.

Leave open when unused.

Vcc Pin

: Supply voltage.

DETAILED DESCRIPTIONS OF TECHNICAL TERMS

RESET OUTPUT

μP will be activated at a valid reset state. These

μP supervisory circuits assert reset to prevent

code execution errors during power-up,

power-down, or brownout conditions.

If a brownout condition occurs (VCC drops below

the reset threshold), RESET goes low. Any time

VCC goes below the reset threshold, the internal

timer resets to zero, and RESET goes low. The

internal timer is activated after VCC returns

above the reset threshold, and RESET remains

RESET is guaranteed to be a logic low for

VTH>VCC>0.9V. Once VCC exceeds the reset

threshold, an internal timer keeps RESET low

for the reset timeout period; after this interval,

low for the reset timeout period.

The manual reset input ( MR ) can also initiate a

reset. AIC812 has an active-high RESET output

that is the inverse of AIC811’s RESET output.

RESET goes high.

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