HYB39S256160T-8B Просмотр технического описания (PDF) - Infineon Technologies

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HYB39S256160T-8B

256 MBit Synchronous DRAM

Infineon Technologies 

256 MBit Synchronous DRAM

HYB39S256400/800/160T

256MBit Synchronous DRAM

Preliminary Information

• High Performance:

-8 -8A -8B Units

fCK 125 125 100 MHz

tCK3

8

8

10

ns

tAC3

6

6

6

ns

tCK2 10

12

15

ns

tAC2

6

6

7

ns

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2, 3, 4

• Programmable Wrap Sequence: Sequential

or Interleave

• Programmable Burst Length:

1, 2, 4, 8

• Multiple Burst Read with Single Write

Operation

• Automatic and Controlled Precharge

Command

• Data Mask for Read / Write control (x4, x8)

• Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 8192 refresh cycles / 64 ms (7,8 µs)

• Random Column Address every CLK

( 1-N Rule)

• Single 3.3V +/- 0.3V Power Supply

• LVTTL Interface versions

• Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

• -8 parts for PC100 2-2-2 operation

-8A parts for PC100 3-2-2 operation

-8B parts for PC100 3-2-3 operation

The HYB39S256400/800/160T are four bank Synchronous DRAM’s organized as 4 banks x 16MBit

x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve

high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches

multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with

INFINEON’s advanced 256MBit DRAM process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

INFINEON Technologies

1

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