MAX1295 Просмотр технического описания (PDF) - Maxim Integrated

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MAX1295

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

Maxim Integrated 

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

tCS

CS

tCSWS

tACQ

tCONV

tWR

tCSWH

WR

tDH

tDS

D7–D0

CONTROL

BYTE

ACQMOD = "0"

INT

HIGH-Z

tINT1

RD

tD0

DOUT

HIGH-Z

HIGH-Z

DATA VALID

tTR

HIGH-Z

Figure 4. Conversion Timing Using Internal Acquisition Mode

Together with the input impedance, this capacitor

forms an RC filter, limiting the ADC’s signal bandwidth.

Input Bandwidth

The MAX1295/MAX1297 T/H stage offers a 250kHz full-

linear and a 3MHz full-power bandwidth. This makes it

possible to digitize high-speed transients and measure

periodic signals with bandwidths exceeding the ADC’s

sampling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended.

Starting a Conversion

Initiate a conversion by writing a control byte that selects

the multiplexer channel and configures the MAX1295/

MAX1297 for either unipolar or bipolar operation. A

write pulse (WR + CS) can either start an acquisition

interval or initiate a combined acquisition plus conver-

sion. The sampling interval occurs at the end of the

acquisition interval. The acquisition mode (ACQMOD)

bit in the input control byte (Table 1) offers two options

for acquiring the signal: an internal and an external

acquisition. The conversion period lasts for 13 clock

cycles in either the internal or external clock or acquisi-

tion mode. Writing a new control byte during a conver-

sion cycle aborts the conversion and starts a new

acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte

with the ACQMOD bit cleared (ACQMOD = 0). This

causes the write pulse to initiate an acquisition interval

whose duration is internally timed. Conversion starts

when this acquisition interval (three external clock

cycles or approximately 1µs in internal clock mode)

ends (Figure 4). Note that, when the internal acquisition

is combined with the internal clock, the aperture jitter

can be as high as 200ps. Internal clock users wishing

to achieve the 50ps jitter specification should always

use external acquisition mode.

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