AN2407 Просмотр технического описания (PDF) - Freescale Semiconductor

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AN2407

Reed Solomon Encoder/Decoder on the StarCore™ SC140/SC1400 Cores, With Extended Examples

Freescale Semiconductor 

Results

15000

Total cycle count

14000

13000

12000

11000

10000

9000

8000

7000

6000

5000

0

2

4

6

8

Figure 8. Average Cycle Count Sum of Decoder Routines, as a Function of nerrors

The assembly code for matrix multiplication contains the potential for one contention in one of the five cycles of

the inner loop, since the table exp_2_bin_extended is accessed twice in the same cycle. The probability per

contention is 1/16. Table 2 and Table 3 depict the results obtained for the ADSL application. The symbol time is

246.4 µsec. Assuming that the DSP runs at 300 MHz, the full processor load is 73,920 cycles. The results are

obtained in the worst case, in which both T and nerrors equal 8.

Encoder

Encoding

routine

TOTAL

Table 2. Encoder Routine

Average Cycle Count

6359

Worst Case Cycle Count

6500

MCPS@300 MHz

24.0

6359

6500

24.0

Decoder

Syndromes

calculation

Berlekamp-

Massey

Roots search

Forney

TOTAL

Table 3. Decoder Routine

Average Cycle Count

5772

Worst Case Cycle Count

5894

3810

3816

4128

587

14,298

4128

590

14,428

MCPS@300 MHz

21.8

14.5

15.6

2.1

54.0

Reed Solomon Encoder/Decoder on the StarCore™ SC140/SC1400 Cores, With Extended Examples, Rev. 1

18

Freescale Semiconductor

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