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AT34C02C-TP25-T Просмотр технического описания (PDF) - Atmel Corporation

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AT34C02C-TP25-T Datasheet PDF : 18 Pages
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WP Connected to GND or Floating
Set RSWP
W
X
Clear RSWP
W
Programmed
Not Programmed
X
Clear RSWP
W
Not Programmed
X
Table 9. WP Connected to Vcc
ACK
No ACK
ACK
Program reversible write protect register (reversible)
STOP - Indicates permanent write protect register is
programmed
Clear (unprogram) reversible write protect register
(reversible)
WP Connected to Vcc
Command
R/W Bit
Permanent Write
Protect Register
PSWP
1010
R
X
1010
W
X
Reversible Write
Protect Register
RSWP
X
X
Acknowledgment
from Device
ACK
ACK
Action from Device
Read array
Device Write Protect
Read
PSWP
R
Programmed
X
Read
PSWP
R
Not Programmed
X
Set PSWP
W
Programmed
X
Set PSWP
W
Not Programmed
X
No ACK
ACK
No ACK
ACK
STOP - Indicates permanent write protect register is
programmed
Read out data don't care. Indicates PSWP register is
not programmed
STOP - Indicates permanent write protect register is
programmed
Cannot program write protect registers
Read
RSWP
R
Read
RSWP
R
Set RSWP
W
Set RSWP
W
Clear
RSWP
W
Clear
RSWP
W
Read
Operations
X
Programmed
X
Not Programmed
X
X
Programmed
Programmed
Not Programmed
X
Not Programmed
X
No ACK
ACK
No ACK
ACK
No ACK
ACK
STOP - Indicates reversible write protect register is
programmed
Read out data don't care. Indicates RSWP register is
not programmed
STOP - Indicates reversible write protect register is
programmed
Cannot program write protect registers
STOP - Indicates permanent write protect register is
programmed
Cannot write to write protect registers
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page.
10 AT34C02C
5242B–SEEPR–01/09

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