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AT48802-16QC

Spread-Spectrum Signal Processor Integrated Circuit

Atmel Corporation 

AT48802

Time Division Duplex Architecture

The AT48802 processor supports a Time Division Duplex

(TDD) mode of operation where the transceiver transmits

information during one time period and receives during an

alternating time period. This architecture has the benefit of

optimizing the frequency channel utilization as the trans-

mit and receive frequencies can be equal to or close to

one another, without spreading at two frequencies that are

wide apart. The chip generates all TDD signals, (including

those signals that account for time delays through the RF

transceiver) that are necessary to implement a full-duplex

voice communication system. All internal timing is derived

from a master external clock. The chip is fully static and

can work at any clock frequency less than 20 MHz. In all

the following discussions the clock rate is assumed to be

15.360 MHz which is available from the companion RF

module.

The 15.360 MHz master clock is internally divided down to

a 7.5 kHz TDD rate, alternating between transmit cycle

and receive cycle. That is, the transmit and receive cycles

last for 66.67µs.

Sleep Mode and Battery Functionality

In most battery applications it is necessary to power down

one end of the communication link except when a call is to

be made. The sleep mode circuits of the AT48802 control

this function.

The sleep mode circuits consist of a timer which runs from

a low frequency (4 kHz) RC oscillator and a set of latches

to interact with the rest of the chip which runs from the high

frequency clock input. The sleep mode circuits also can

also disable and protect the I/O’s of the high frequency

circuits. The protected mode is such that the outputs are

three-stated and the input is floating. In addition, the sleep

control section has a DC power control output which can

be used to shutdown external circuits VCC.

The chip should always be connected to VCC in order for

the sleep mode to be usable; the sleep mode circuits are

alive and running as long as VCC is applied, however their

power drain is extremely small.

The sleep circuits will wake-up the chip, and other circuits

if desired, in any one of three ways.

1. Time-out from the 4 kHz Oscillator will happen about

2 seconds (one half cycle of divided by 214 ) after go-

ing to sleep. Then the remote set could, for example,

briefly listen for an incoming call using narrowband re-

ception (which has little or no acquisition time), and

listen for a predetermined tone with a very narrow-

band filter. For different wake-up periods the value of

the C can be changed.

2. If the INTERCOM input is activated. The edge sense

is programmable at R6 b7.

3. If the FLIPSW input is activated. The edge sense is

programmable at R11 b7.

When the chip wakes up it stores information about the

reason for wake-up in the I/O Registers at R14 b0-2 so the

microprocessor can respond in a suitable way. The edge

sense for FLIPSW and INTERCOM are programmed at

R14 b4-5. (Note: Throughout this document “Rx by”

means Register x bit y; x is hexadecimal.)

Once the chip is awake, only the microprocessor can put

it back into sleep mode. It does this through the bus port

at R0 b7. The OPERATE bit must be set before the com-

mand to STANDBY can be recognized. If the chip is

awake and the user activates the INTERCOM or FLIPSW

inputs, then the microprocessor can sense these actions

at R14 b4-5.

Figure 1. Sleep Mode Arrangement

VCC

High Speed I/Os

High Speed

Processing

Circuits

Sleep Mode Circuits

High Speed I/Os

(Operate/!Standby

and Wake 0, Wake 1)

2-5

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