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BD8179MUV Просмотр технического описания (PDF) - ROHM Semiconductor

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BD8179MUV Datasheet PDF : 13 Pages
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BD8179MUV
Technical Note
Under Voltage Lock Out (UVLO)
The UVLO circuit compares the input voltage at IN with the UVLO threshold (2.4V rising, 2.2V falling, typ) to ensure the input
voltage is high enough for reliable operation.
The 200mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO
rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the
main step-up regulator, turns off the linear-regulator outputs, and disables the Gate Shading controller.
Thermal Shut Down (TSD)
The TSD prevents excessive power dissipation from overheating the BD8179MUV. When the junction temperature exceeds
Tj=175(Typ), a thermal sensor immediately activates. The fault protection, which shuts down all outputs except the
reference, allowing the device to cool down. Once the device cools down by approximately 15reactivate the device.
Over Voltage Protection (OVP)
The Step up DC/DC converter has OVP circuit.
The OVP circuit compares the input Voltage at SUP with the OVP threshold (19V rising, 18.5V falling, Typ) to protect the step
up DC/DC output exceed the absolute maximum voltage. Once the SUP Voltage exceeds the OVP rising threshold, turn off
the main Step-up regulator.
Then, the SUP Voltage falls bellow the OVP falling threshold,reactivate the main Step-Up regulator.
Over Current Protection (OCP)
The Step-Up DC/DC converter, linear-regulator and Operational Amplifier have OCP circuit respectively.
The OCP circuit restricts to load current, when an OCP activated, one’s own output only restricted.
However, if the output continue to overload, the device is possible to activate thermal shutdown or short current protection.
Timer Latch Mode Short Current Protection (SCP)
BD8179MUV has SCP circuit feature to prevent the large current flowing when the output is shorted to GND.
This function is monitoring VMAIN, VGON, and VGOFF Voltage and starts the timer when at least one of the outputs operating
properly (when the output voltage was lower than expected).
After 150ms (Typ.) of this abnormal state, the device will shutdown the all outputs and latch the state.
VMAIN
FB
VGON
FBP
VGOFF
FB N
150ms typ
Counter
reset
all outputs
shut down.
Fig.13 SCP Block Diagram
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
7/12
2009.07 - Rev.B

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