AS4LC1M16S0-8TC Просмотр технического описания (PDF) - Alliance Semiconductor

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AS4LC1M16S0-8TC

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

®

Command

Auto refresh

Self refresh

Pin settings

Description

SDRAM storage cells must be refreshed every 64 ms to maintain data

integrity. Use the auto refresh command to accomplish the refreshing

of all rows in both banks of the SDRAM. The row address is provided

CS = RAS = CAS = low; WE = by an internal counter which increments automatically. Auto refresh

CKE = high; A0~A11 = don’t can only be asserted when both banks are idle and the device is not in

care

the power down mode. The time required to complete the auto refresh

operation is tRC(min). Use NOPs in the interim until the auto refresh

operation is complete. Both banks will be in the idle state after this

operation.

Self refresh is another mode for refreshing SDRAM cells. In this mode,

refresh address and timing are provided internally. Self refresh entry is

allowed only when both banks are idle. The internal clock and all input

CS = RAS = CAS = CKE = low; buffers with the exception of CKE are disabled in this mode. Exit self

WE = high; A0~A11 = don’t refresh by restarting the external clock and then asserting CKE high.

care

NOPs must follow for a time of tRC(min) for the SDRAM to reach the

idle state where normal operation is allowed. If burst auto refresh is

used in normal operation, burst 2048 auto refresh cycles immediately

after exiting self refresh.

Initialize and load mode register

T0

T1

Tn

CLK

tCK

tCH

tCKS tCKH

CKE

Tm

tCL

Tp+1

Tp+2

COMMAND

tCMH

NOP

tCMS

PRECHARGE

ALL

AUTO REFRESH

NOP NOP

AUTO REFRESH

NOP NOP

LOAD MODE

REGISTER

NOP

Tp+3

ACTIVE

DQM*

ADDRESS

High Z

DQ

T=200µs

(min)

A10=HIGH

tRP

tAS

tAH

CODE

BANK ROW

tRCAR

tMRD

Power up:

VDD and

CLK stable.

Precharge

all banks.

AUTO REFRESH

(8 AUTO REFRESH

CYCLES)

* DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

† The Mode Register may be loaded prior to the auto refresh cycles if desired.

ƒ Outputs are guaranteed High-Z after command is issued.

Program Mode Register†ƒ

5/21/01; v.1.1

Alliance Semiconductor

P. 12 of 29

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