AS7C256-12JI Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C256-12JI Datasheet PDF : 9 Pages
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AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5V
+3.0V
90%
90%
10%
GND
2 ns
10%
Figure A: Input pulse
DRXW
255Ω
480Ω
C(14)
GND
Figure B: Output loDG
AS7C256
AS7C3256
Thevenin equivalent
168Ω
DRXW
+1.72V (5V and 3.3V)
+3.3V
DRXW
350Ω
320Ω
C(14)
GND
Figure C: Output load
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is High for read cycle.
7 CE and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
9/18/01; v.1.6
Alliance Semiconductor
P. 6 of 9
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