CMX605P3(2001) Просмотр технического описания (PDF) - CML Microsystems Plc

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производитель

CMX605P3
(Rev.:2001)

Digital Line to POTS Interface

CML Microsystems Plc 

Digital Line to POTS Interface

CMX605

1.5.7 DTMF Tone Decoder

This block is enabled or disabled by bit 5 of the SETUP register. If disabled, bit 0 to bit 5 of the STATUS

Register are set to ‘0’ and no interrupts are generated. When enabled (set to ‘1’), a status change of the

decoder will generate an interrupt and bit 5 of the STATUS Register will be set to ‘1’. The validity of the

data is indicated by bit 4 of the STATUS Register. The decode truth table is shown below:

STATUS Register Bits 0 - 3

Bit 3 Bit 2 Bit 1

(D3)

(D2)

(D1)

0

0

0

0

0

0

0

0

1

0

0

1

0

1

0

0

1

0

0

1

1

0

1

1

1

0

0

1

0

0

1

0

1

1

0

1

1

1

0

1

1

0

1

1

1

1

1

1

Bit 0

(D0)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DTMF Tone

Lower Frequency

(Hz)

941

697

697

697

770

770

770

852

852

852

941

941

941

697

770

852

Pairs

Upper Frequency

(Hz)

1633

1209

1336

1477

1209

1336

1477

1209

1336

1477

1336

1209

1477

1633

1633

1633

Keypad

Legend

D

1

2

3

4

5

6

7

8

9

0

*

#

A

B

C

A status change of the decoder and the generation of an interrupt will occur both when a tone is first

decoded and also when a tone, which was previously present, is no longer decoded. In the latter case,

Bit 4 of the STATUS Register will be set to “0” to indicate that no tone was detected.

© 2001 Consumer Microcircuits Limited

12

D/605/6

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