A386DX Просмотр технического описания (PDF) - Intel

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A386DX

32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT

Intel 

Intel386TM DX MICROPROCESSOR

10 REVISION HISTORY

This Intel386 DX data sheet version -005 contains updates and improvements to previous versions A revi-

sion summary is listed here for your convenience

The sections significantly revised since version -001 are

296

Sequence of exception checking table added

297

Instruction restart revised

2 11 2

TLB testing revised

2 12

Debugging support revised

31

LOCK prefix restricted to certain instructions

4433

I O privilege level and I O permission bitmap added

Figures 4-15a 4-15b

I O permission bitmap added

464

Protection and I O permission bitmap revised

466

Entering and leaving virtual 8086 mode through task switches trap and interrupt

gates and IRET explained

56

Self-test signature stored in EAX

58

Coprocessor interface description added

581

Software testing for coprocessor presence added

Table 6-3

PGA package thermal characteristics added

7

Designing for ICE-Intel386 revised

Figures 7-8 7-9 7-10

ICE-Intel386 clearance requirements added

6234

Encoding of 32-bit address mode with no ‘‘sib’’ byte corrected

The sections significantly revised since version -002 are

Table 2-5

Interrupt vector assignments updated

Figure 4-15a

Bit map offset must be less than or equal to DFFFH

Figure 5-28

Intel386 DX outputs remain in their reset state during self-test

57

Component and revision identifier history updated

94

20 MHz D C specifications added

95

16 MHz A C specifications updated 20 MHz A C specifications added

Table 6-1

Clock counts updated

The sections significantly revised since version -003 are

Table 2-6b

Interrupt priorities 2 and 3 interchanged

298

Double page faults do not raise double fault exception

Figure 4-5

5434

Maximum-sized segments must have segments Base11 0 e 0

BS16 timing corrected

Figures 5-16 5-17

BS16 timing corrected BS16 must not be asserted once NA has been

5-19 5-22

sampled asserted in the current bus cycle

95

16 MHz and 20 MHz A C specifications revised All timing parameters are now

guaranteed at 1 5V test levels The timing parameters have been adjusted to

remain compatible with previous 0 8V 2 0V specifications

137

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