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CY8C20111

CapSense® Express™ – One Button and Two Button Capacitive Controllers

Cypress Semiconductor 

CY8C20111, CY8C20121

Table 12. 2.7-V AC GPIO Specifications

Parameter

tRise

tFall

Description

Rise time, strong mode,

Cload = 50 pF

Fall time, strong mode,

Cload = 50 pF

Min

Max Unit

Notes

15

100

ns VDD = 2.4 V to 2.90 V, 10% to 90%

10

70

ns VDD = 2.4 V to 2.90 V, 10% to 90%

AC I2C Specifications

Table 13. AC I2C Specifications

Parameter

Description

FSCLI2C

SCL clock frequency

Standard Mode

Min

Max

0

100

tHDSTAI2C

Hold time (repeated) START

condition. After this period, the

4.0

–

first clock pulse is generated

tLOWI2C

LOW period of the SCL clock

4.7

–

tHIGHI2C

HIGH period of the SCL clock

4.0

–

tSUSTAI2C

Setup time for a repeated START

4.7

condition

–

tHDDATI2C

Data hold time

0

–

tSUDATI2C

Data setup time

250

–

tSUSTOI2C

Setup time for STOP condition

4.0

–

tBUFI2C

BUS free time between a STOP

4.7

and START condition

–

tSPI2C

Pulse width of spikes suppressed

–

by the input filter

–

Fast Mode

Min

Max

0

400

0.6

–

Units

Notes

kbps Fast mode not

supported for

VDD < 3.0 V

µs

1.3

–

µs

0.6

–

µs

0.6

–

µs

0

–

µs

100

–

ns

0.6

–

µs

1.3

–

µs

0

50

ns

Figure 17. Definition of Timing for Fast/Standard Mode on the I2C Bus

I2C_SDA

I2C_SCL

TSUDATI2C

THDSTAI2C

THDDATI2CTSUSTAI2C

TSPI2C

TBUFI2C

THIGHI2C TLOWI2C

S

START Condition

TSUSTOI2C

Sr

P

S

Repeated START Condition

STOP Condition

Document Number: 001-53516 Rev. *H

Page 34 of 44

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