CY8C36(2010) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY8C36
(Rev.:2010)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 3: CY8C36 Family Datasheet

Figure 2-2. 48-pin QFN Part Pinout[7]

(GPIO) P2[6] 1

(GPIO) P2[7] 2

Vssb 3

Ind 4

Vboost 5

Vbat 6

(GPIO, TMS, SWDIO) P1[0] 7

(GPIO, TCK, SWDCK) P1[1] 8

(GPIO, Configurable XRES) P1[2] 9

(GPIO, TDO, SWV) P1[3] 10

(GPIO, TDI) P1[4] 11

(GPIO, nTRST) P1[5] 12

Lines show

Vddio to I/O

supply

association

QFN

( Top View)

36 P0[3] (OpAmp0-/Extref0, GPIO)

35 P0[2] (OpAmp0+, GPIO)

34 P0[1] (OpAmp0out, GPIO)

33 P0[0] (OpAmp2out, GPIO)

32 P12[3] (SIO)

31 P12[2] (SIO)

30 Vdda

29 Vssa

28 Vcca

27 P15[3] (GPIO, kHz XTAL: Xi)

26 P15[2] (GPIO, kHz XTAL: Xo)

25 P12[1] (SIO, I2C1: SDA)

Notes

6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Document Number: 001-53413 Rev. *I

Page 6 of 112

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