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CY8C38

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®3: CY8C38 Family Data Sheet

one bit error and detect two bit errors per 8 bytes of firmware

memory; an interrupt can be generated when an error is

detected. The Flash output is 9 bytes wide with 8 bytes of data

and 1 byte of ECC data.

Flash programming is performed through a special interface and

preempts code execution out of Flash. The Flash programming

interface performs Flash erasing, programming and setting code

protection levels. Flash In System Serial Programming (ISSP),

typically used for production programming, is possible through

both the SWD and JTAG interfaces. In-system programming,

typically used for bootloaders, is also possible using serial inter-

faces such as I2C, USB, UART, and SPI, or any communications

protocol.

5.3 Flash Security

All PSoC devices include a flexible Flash protection model that

prevents access and visibility to on-chip Flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of ECC or configu-

ration data. A total of up to 256 blocks are provided on 64 KB

Flash devices.

The device offers the ability to assign one of four protection

levels to each row of Flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete Flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a boot loader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security which

permanently disables all test, programming, and debug ports,

protecting your application from external access (see the

“Device Security” section on page 58). For more information on

how to take full advantage of the security features in PSoC, see

the PSoC 3 TRM.

Table 5-1. Flash Protection

Protection

Setting

Allowed

Not Allowed

Unprotected External read and write -

+ internal read and write

Factory

Upgrade

External write + internal External read

read and write

Field Upgrade Internal read and write External read and

write

Full Protection Internal read

External read and

write + internal write

Cypress products meet the specifications contained in their

particular Cypress data sheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are guaran-

teeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

5.4 EEPROM

PSoC EEPROM memory is a byte addressable nonvolatile

memory. The CY8C38 has up to 2 KB of EEPROM memory to

store user data. Reads from EEPROM are random access at the

byte level. Reads are done directly; writes are done by sending

write commands to an EEPROM programming interface. CPU

code execution can continue from Flash during EEPROM writes.

EEPROM is erasable and writeable at the row level. The

EEPROM is divided into 128 rows of 16 bytes each.

The CPU can not execute out of EEPROM. There is no ECC

hardware associated with EEPROM. If ECC is required it must

be handled in firmware.

5.5 External Memory Interface

CY8C38 provides an External Memory Interface (EMIF) for

connecting to external memory devices. The connection allows

read and write accesses to external memories. The EMIF

operates in conjunction with UDBs, I/O ports, and other

hardware to generate external memory address and control

signals.

Figure 5-1 is the EMIF block diagram. The EMIF supports

synchronous and asynchronous memories. The CY8C38

supports only one type of external memory device at a time.

External memory can be accessed via the 8051 xdata space; up

to 24 address bits can be used. See “xdata Space” section on

page 21. The memory can be 8 or 16 bits wide.

Disclaimer

Note the following details of the Flash code protection features

on Cypress devices.

Document Number: 001-11729 Rev. *I

Page 18 of 100

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