CY8C38 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY8C38

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®3: CY8C38 Family Data Sheet

Clock Divider SFR

The CPU clock divider allows the CPU to run at speeds that are

divisors of the BUS clock speed. Users can specify CPU clock

speed by configuring the CPUCLK_DIV register in the user SFR

space at address 0xA1:. Using this register, the CPU clock can

be dynamically slowed down or speeded up, which allows finer

control of power usage.

Table 5-3. Clock Divider Settings

CPUCLK_DIV

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

CPU Clock Frequency

clk_cpu = clk_bus

clk_cpu = clk_bus/2

clk_cpu = clk_bus/3

clk_cpu = clk_bus/4

clk_cpu = clk_bus/5

clk_cpu = clk_bus/6

clk_cpu = clk_bus/7

clk_cpu = clk_bus/8

0x08

0x09

0x0A

0x0B

0x0C

clk_cpu = clk_bus/9

clk_cpu = clk_bus/10

clk_cpu = clk_bus/11

clk_cpu = clk_bus/12

clk_cpu = clk_bus/13

0x0D

0x0E

0x0F

clk_cpu = clk_bus/14

clk_cpu = clk_bus/15

clk_cpu = clk_bus/16

5.6.3.1 xdata Space

The 8051 xdata space is 24-bit, or 16 MB in size. The majority of

this space is not “external”—it is used by on-chip components.

See Table 5-4. External, that is, off-chip, memory can be

accessed using the EMIF. See External Memory Interface.

Table 5-4. XDATA Data Address Map

Address Range

Purpose

0x00 0000 - 0x00 1FFF SRAM

0x00 4000 - 0x00 42FF Clocking, PLLs, and oscillators

0x00 4300 - 0x00 43FF Power management

0x00 4400 - 0x00 44FF Interrupt controller

0x00 4500 - 0x00 45FF Ports interrupt control

0x00 4700 - 0x00 47FF System performance controller

0x00 4900 - 0x00 49FF I2C controller

0x00 4E00 - 0x00 4EFF Decimator

0x00 4F00 - 0x00 4FFF Fixed timer/counter/PWMs

0x00 5000 - 0x00 51FF General purpose I/Os

0x00 5300 - 0x00 530F Output port select register

0x00 5400 - 0x00 54FF External Memory Interface control

registers

0x00 5800 - 0x00 5FFF Analog Subsystem interface

0x00 6000 - 0x00 60FF USB controller

0x00 6400 - 0x00 6FFF UDB configuration

0x00 7000 - 0x00 7FFF PHUB configuration

0x00 8000 - 0x00 8FFF EEPROM

0x00 A000 - 0x00 A400 CAN

0x00 C000 - 0x00 C800 Digital Filter Block

0x01 0000 - 0x01 FFFF Digital Interconnect configuration

0x03 0000 - 0x03 01FF Reserved

0x05 0220 - 0x05 02F0 Debug controller

0x08 0000 - 0x08 1FFF Flash ECC bytes

0x80 0000 - 0xFF FFFF External Memory Interface

Document Number: 001-11729 Rev. *I

Page 21 of 100

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