CYRF69213(2007) Просмотр технического описания (PDF) - Cypress Semiconductor

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CYRF69213
(Rev.:2007)

Programmable Radio on Chip Low Power

Cypress Semiconductor 

CYRF69213

Table 33.CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

USB CLK/2

Disable

USB CLK

Select

Reserved

CPUCLK Se-

lect

Read/Write

–

R/W

R/W

–

–

–

–

R/W

Default

0

0

0

0

0

0

0

0

Bit 7

Reserved

Bit 6

USB CLK/2 Disable

This bit only affects the USBCLK when the source is the external crystal oscillator. When the USBCLK source is the Internal

24-MHz Oscillator, the divide by two is always enabled

0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24-MHz Oscillator is used, or when the

external source is used with a 24-MHz clock

1 = USBCLK is undivided. Use this setting only with a 12-MHz external clock

Bit 5

USB CLK Select

This bit controls the clock source for the USB SIE

0 = Internal 24-MHz Oscillator. With the presence of USB traffic, the Internal 24-MHz Oscillator can be trimmed to meet the USB

requirement of 1.5% tolerance (see Table 35)

1 = External clock—Internal Oscillator is not trimmed to USB traffic.

Proper USB SIE operation requires a 12-MHz or 24-MHz clock accurate to <1.5%

Bits 4:1

Reserved

Bit 0

CPU CLK Select

0 = Internal 24-MHz Oscillator

1 = External clock—External clock at CLKIN (P0.0) pin

Note The CPU speed selection is configured using the OSC_CR0 Register (Table 34)

Document #: 001-07552 Rev. *B

Page 23 of 85

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