MT48LC128M4A2P-7EC Просмотр технического описания (PDF) - Micron Technology

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производитель

MT48LC128M4A2P-7EC

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 35: Clock Suspend Mode

T0

CLK

T1

T2

T3

tCK

tCL

tCH

tCKS tCKH

CKE

tCKS tCKH

tCMS tCMH

COMMAND

READ

NOP

NOP

T4

T5

T6

T7

T8

NOP

NOP

NOP

WRITE

DQM/

DQML, DQMU

A0–A9,

A11, A12

A10

BA0, BA1

tAS tAH

COLUMN m 2

tAS tAH

tAS tAH

BANK

tCMS tCMH

COLUMN e2

BANK

tAC

tAC

tOH

tHZ

tDS tDH

DQ

DOUT m

DOUT m + 1

Din e

tLZ

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

T9

NOP

Din + 1

Don’t Care

Undefined

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

51

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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