MT48LC128M4A2P-7EC Просмотр технического описания (PDF) - Micron Technology

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Компоненты Описание

производитель

MT48LC128M4A2P-7EC

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 45: WRITE – Without Auto Precharge

T0

T1

T2

T3

CLK

tCK

tCL

tCH

tCKS tCKH

CKE

tCMS tCMH

COMMAND

ACTIVE

NOP

WRITE

NOP

DQM/

DQML, DQMU

A0–A9,

A11, A12

A10

BA0, BA1

tAS tAH

ROW

tAS tAH

ROW

tAS tAH

BANK

tCMS tCMH

COLUMN m 2

DISABLE AUTO PRECHARGE

BANK

DQ

tRCD

tRAS

tRC

tDS tDH

DIN m

tDS tDH

DIN m + 1

T4

NOP

tDS tDH

DIN m + 2

T5

NOP

tDS tDH

DIN m + 3

T6

NOP

t WR 3

T7

T8

PRECHARGE

NOP

ALL BANKs

SINGLE BANK

BANK

tRP

T9

ACTIVE

ROW

ROW

BANK

Don’t Care

Notes:

1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-

quency.

3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

61

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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