LTC1282(Rev0) Просмотр технического описания (PDF) - Linear Technology

Номер в каталоге

Компоненты Описание

производитель

LTC1282
(Rev.:Rev0)

3V 140ksps 12-Bit Sampling A/D Converter with Reference

Linear Technology 

LTC1282

UU

W

FU TIO AL BLOCK DIAGRA

CSAMPLE

SAMPLE

AIN

HOLD

SAMPLE

COMPARATOR

–

+

VDD VSS (–3V FOR BIPOLAR MODE,

AGND FOR UNIPOLAR MODE)

VREF(OUT)

1.2V

REFERENCE

12-BIT

CAPACITIVE

DAC

12 SUCCESSIVE

12

APPROXIMATION

REGISTER

AGND DGND

INTERNAL

CLOCK

CONTROL

LOGIC

OUTPUT

LATCHES

D11

•

•

•

D0/8

BUSY

CS

RD

HBEN

LTC1282 • FBD

APPLICATI S I FOR ATIO

CONVERSION DETAILS

The LTC1282 uses a successive approximation and an

internal sample-and-hold circuitry to convert an analog

signal to a 12-bit parallel or 2-byte output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. Please refer to the Digital Interface section

for the data format.

Conversion start is controlled by the CS, RD and HBEN

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset and the three-state data

outputs are enabled. Once a conversion cycle has begun

it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor during the sample phase, and the comparator

offset is nulled by the feedback switch. In this sample

phase, a minimum delay of 1.0µs will provide enough time

for the sample-and-hold capacitor to acquire the analog

signal. During the convert phase, the comparator feed-

back switch opens, putting the comparator into the com-

pare mode. The input switch switches CSAMPLE to ground,

injecting the analog input charge to the summing junction.

This input charge is successively compared with the

binary-weighted charges supplied by the capacitive DAC.

Bit decisions are made by the high speed comparator. At

the end of a conversion, the DAC output balances the AIN

input charge. The SAR contents (a 12-bit data word) which

represent the AIN are loaded into the 12-bit latch.

SAMPLE

AIN

HOLD

CSAMPLE

CDAC

DAC

VDAC

SAMPLE

SI

–

+

COMPARATOR

S

A

R

Figure 1. AIN Input

LTC1282 • F01

12-BIT

LATCH

10

Share Link: