AC CHARACTERISTICS
PRELIMINARY
Addresses
CE#
OE#
WE#
DQ7
DQ0–DQ6
tRC
VA
tACC
tCE
tCH
tOEH
tOE
tDF
tOH
Complement
Status Data
VA
Complement True
Status Data True
VA
Valid Data
Valid Data
High Z
High Z
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle .
21445B-16
Figure 11. Data# Polling Timings (During Embedded Algorithms)
Addresses
CE#
OE#
WE#
DQ6/DQ2
tRC
VA
tACC
tCE
tCH
tOE
tOEH
tDF
High Z
tOH
Valid Status
(first read)
VA
Valid Status
(second read)
VA
VA
Valid Status
(stops toggling)
Valid Data
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21445B-17
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
Am29F040B
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