FM93C46A Просмотр технического описания (PDF) - Fairchild Semiconductor

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производитель

FM93C46A

1K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)

Fairchild Semiconductor 

Timing Diagrams (Continued)

ERASE CYCLE (ERASE)

tCS

CS

SK

DI

1 1 1 An An-1

A1 A0

tWP

Start Opcode

Address

Bit

Bits(2) High - Z Bits(6/7)

DO

93C46A (ORG=1; An=A5):

Address bits pattern -> A5-A4-A3-A2-A1-A0; User defined

Busy

93C46A (ORG=0; An=A6):

Address bits pattern -> A6-A5-A4-A3-A2-A1-A0; User defined

Ready

ERASE ALL CYCLE (ERAL)

tCS

CS

SK

DI

1 0 0 An An-1

A1 A0

tWP

Start Opcode

Address

Bit

Bits(2) High - Z Bits(6/7)

DO

Ready

Busy

93C46A (ORG=1; An=A5):

Address bits pattern -> 1-0-x-x-x-x; (x -> Don’t Care, can be 0 or 1)

93C46A (ORG=0; An=A6):

Address bits pattern -> 1-0-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)

CLEARING READY STATUS

CS

SK

DI

High - Z

DO

Busy

Ready

Start

Bit

High - Z

Note: This Start bit can also be part of a next instruction. Hence the cycle

can be continued(instead of getting terminated, as shown) as if a new

instruction is being issued.

FM93C46A Rev. C.1

10

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