FS6377 Просмотр технического описания (PDF) - ON Semiconductor

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FS6377

Programmable 3-PLL Clock Generator IC

ON Semiconductor 

FS6377

Figure 15: PLL Screen

For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as

small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an

optimal 50 percent duty cycle.

Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv

value in Solution #7 into post divider A and switches mux A to take the output of PLL A.

The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that

mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.

Repeat the steps for PLL B.

PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected

by the logic level on the SEL_CD pin, as are the post dividers C and D.

Figure 16: Post Divider Menu

Rev. 4 | Page 23 of 24 | www.onsemi.com

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