HI-8588 Просмотр технического описания (PDF) - Holt Integrated Circuits
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HI-8588 Datasheet PDF : 6 Pages
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HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
SQ
LATCH
R
TEST
TEST
TESTA
TEST
TEST
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
TESTA ' TESTB
ROUTB
TESTA ' TESTB
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8588 interfacing an ARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
HARDWIRE
OR
{
DRIVE FROM LOGIC
ARINC
Channel
ARINC
Channel
5V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8588
RINA
3
RINB
5
15V
1
8
SLP1.5 V+
6 TXAOUT
TX1IN 3
7 HI-8586 2
TXBOUT
TX0IN
GND V-
45
-15V
FIGURE 2 - APPLICATION DIAGRAM
RXD1
RXD0
HI-6010
8 BIT BUS
TXD1
TXD0
HOLT INTEGRATED CIRCUITS
2
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