HT66F016 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT66F016

Enhanced Flash MCU with EEPROM

Holtek Semiconductor 

HT66F016/HT66F017/HT68F016/HT68F017

HT66F016R/HT66F017R/HT68F016R/HT68F017R

Flash Program Memory

The Program Memory is the location where the user

code or program is stored. For this device series the

Program Memory is Flash type, which means it can be

programmed and re-programmed a large number of

times, allowing the user the convenience of code modifi-

cation on the same device. By using the appropriate

programming tools, these Flash devices offer users the

flexibility to conveniently debug and develop their appli-

cations while also offering a means of field programming

and updating.

Structure

The Program Memory has a capacity of 2K´16 bits. The

Program Memory is addressed by the Program Counter

and also contains data, table information and interrupt

entries. Table data, which can be setup in any location

within the Program Memory, is addressed by a separate

table pointer register.

Device

HT66F016, HT68F016

HT66F017, HT68F017

Capacity

1K´16

2K´16

0000H

0004H

R eset

In te rru p t

V e c to r

03FFH

07FFH

1 6 b its

Program Memory Structure

Special Vectors

Within the Program Memory, certain locations are re-

served for the reset and interrupts. The location 000H is

reserved for use by the device reset for program initialis-

ation. After a device reset is initiated, the program will

jump to this location and begin execution.

Look-up Table

Any location within the Program Memory can be defined

as a look-up table where programmers can store fixed

data. To use the look-up table, the table pointer must

first be setup by placing the address of the look up data

to be retrieved in the table pointer register, TBLP and

TBHP. These registers define the total address of the

look-up table.

After setting up the table pointer, the table data can be

retrieved from the Program Memory using the

²TABRD[m]² or ²TABRDL[m]² instructions, respectively.

When the instruction is executed, the lower order table

byte from the Program Memory will be transferred to the

user defined Data Memory register [m] as specified in

the instruction. The higher order table data byte from the

Program Memory will be transferred to the TBLH special

register. Any unused bits in this transferred higher order

byte will be read as ²0².

The accompanying diagram illustrates the addressing

data flow of the look-up table.

Lastpage or

T B H P R e g is te r

T B L P R e g is te r

P ro g ra m M e m o ry

D a ta

1 6 b its

R e g is te r T B L H

H ig h B y te

U s e r S e le c te d

R e g is te r

L o w B y te

Table Program Example

The following example shows how the table pointer and

table data is defined and retrieved from the

microcontroller. This example uses raw table data lo-

cated in the Program Memory which is stored there us-

ing the ORG statement. The value at this ORG

statement is ²700H² which refers to the start address of

the last page within the 2K words Program Memory of

the device. The table pointer is setup here to have an ini-

tial value of ²06H². This will ensure that the first data

read from the data table will be at the Program Memory

address ²706H² or 6 locations after the start of the last

page. Note that the value for the table pointer is refer-

enced to the first address of the present page if the

²TABRD [m]² instruction is being used. The high byte of

the table data which in this case is equal to zero will be

transferred to the TBLH register automatically when the

²TABRD [m]² instruction is executed.

Because the TBLH register is a read-only register and

cannot be restored, care should be taken to ensure its

protection if both the main routine and Interrupt Service

Routine use table read instructions. If using the table

read instructions, the Interrupt Service Routines may

change the value of the TBLH and subsequently cause

errors if used again by the main routine. As a rule it is

recommended that simultaneous use of the table read

instructions should be avoided. However, in situations

where simultaneous use cannot be avoided, the inter-

rupts should be disabled prior to the execution of any

main routine table-read instructions. Note that all table

related instructions require two instruction cycles to

complete their operation.

Rev. 1.40

19

November 22, 2016

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