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IS75V16F128GS32

3.0 Volt Multi-Chip Package (MCP) — 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

Integrated Silicon Solution 

IS75V16F128GS32

ISSI ®

GENERAL DESCRIPTION

This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM.

Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152

words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,

Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be

accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively.

The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.

The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM

programmer.

The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the

PSRAM access time is 65ns.

Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on

each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then

immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same

chip, with zero latency.

MCP BLOCK DIAGRAM

A0-A21

RESET1

CEf1

VCCf1 GND

64-MBIT

Flash Memory

(Flash 1)

RY/BY1

A0-A21

A0-A21

WP/ACC

RESET2

CEf2

A0-A20

LB

UB

WE

OE

CE1r

CE2r

PE

VCCf2 GND

32-MBIT

Flash Memory

(Flash 2)

RY/BY2

DQ0-DQ15

VCCr GND

32-MBIT

PSRAM

2

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00D

03/24/03

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