ISL22349(2006) Просмотр технического описания (PDF) - Intersil

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производитель

ISL22349
(Rev.:2006)

Quad Digitally Controlled Potentiometers (XDCP™)

Intersil 

ISL22349

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MIN (NOTE 5) MAX

UNIT

tHD:A A2, A1 and A0 Hold Time

After STOP condition

600

ns

NOTES:

5. Typical values are for TA = +25°C and 3.3V supply voltage.

6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW)0/LSB.

8. FS error = [V(RW)127 – VCC]/LSB.

9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.

10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127.

11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

12.

TCV

=

-------M-----a----x----(--V----(---R-----W------)--i--)---–-----M-----i--n----(--V-----(--R-----W------)--i--)------ × ----1----0---6----- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

[Max(V(RW)i) + Min(V(RW)i)] ⁄ 2 165°C minimum value of the resistance over the temperature range.

13. This parameter is not 100% tested.

14. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile

write cycle.

SDA vs SCL Timing

tF

tHIGH

tLOW

tR

tsp

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tSU:DAT

tHD:STA

tHD:DAT

tAA tDH

tSU:STO

tBUF

A0, A1, and A2 Pin Timing

SCL

START

CLK 1

STOP

SDA

A0, A1, OR A2

tSU:A

tHD:A

6

FN6331.2

September 15, 2006

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