ISL6227 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

ISL6227

Dual Mobile-Friendly PWM Controller with DDR Option

Intersil 

Block Diagram

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

VCC

ADAPTIVE DEAD-TIME

DIODE EMULATION

V/I SAMPLE TIMING

PWM/HYS TRANSITION

MODE CHANGE COMP 1

HYSTERETIC COMPARATOR 1

SAME STATE FOR

8 CLOCK CYCLES

REQUIRED TO CHANGE

PWM OR HYS MODE

ΔVHYS=15mV

VSEN1

300kΩ

500kΩ

SOFT1

+ 0.9V

REF

1MΩ

15pF

1.25pF

4.4kΩ

ERROR AMP 1

ISEN1 140Ω

CURRENT

SAMPLE

OCSET1

CURRENT

SAMPLE

+ 0.9V REFERENCE

PG1 EN1 VOUT1

VCC GND

VOUT2 EN2 REF/PG2

DDR=0 DDR=1

OV UV

PGOOD

VOLTS/SEC

CLAMP

PWM1

POR

ENABLE

BIAS SUPPLIES

REFERENCE

FAULT LATCH

SOFT START

DDR MODE

CONTROL

OC1 DDR OC2

OV UV

PGOOD

VOLTS/SEC

CLAMP

PWM2

DUTY CYCLE RAMP GENERATOR

PWM CHANNEL PHASE CONTROL

DDR EN1 EN2

VIN

CH1CH2 φ

0 11

0 ⇔ 24.0V

180º

4.2 < VIN < 24.0V

90º

111

VIN < 4.2

0º

ADAPTIVE DEAD-TIME

DIODE EMULATION

V/I SAMPLE TIMING

PWM/HYS TRANSITION

BOOT2

UGATE2

PHASE2

PGND2

LGATE2

VCC

MODE CHANGE COMP 2

SAME STATE FOR

8 CLOCK CYCLES

REQUIRED TO CHANGE

PWM OR HYS MODE

HYSTERETIC COMPARATOR 2

ΔVHYS=15mV

15pF

1MΩ

4.4kΩ

1.25pF

ERROR AMP 2

500kΩ

300kΩ

(200kΩ, DDR=1)

VSEN2

SOFT2

CURRENT

SAMPLE

0.9V REFERENCE +

DDR=0

+

0.9V

REF

DDR=1

140Ω ISEN2

CURRENT

SAMPLE

OCSET2

DDR=0

DDR=1

OC1

OC2

1/2.9

OCSET1

1/33.1

ISEN1

VIN

SAME STATE FOR

8 CLOCK CYCLES

REQUIRED TO LATCH

OVERCURRENT FAULT

DDR

VCC

SAME STATE FOR

8 CLOCK CYCLES

REQUIRED TO LATCH

OVERCURRENT FAULT

1/33.1

ISEN2

1/2.9

OCSET2

DDR VREF

BUFFER AMP

DDR VTT

REFERENCE

Share Link: