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ISP1109BS Просмотр технического описания (PDF) - Philips Electronics

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ISP1109BS Datasheet PDF : 59 Pages
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Philips Semiconductors
ISP1109
USB transceiver with carkit support
If the Power-down is because of the setting of register bit PWR_DN in the Mode
Control register, the bias will be enabled if the VBUS voltage goes above the
SESS_VLD threshold. Note: In this case, make sure bit SESS_VLD_IEH in the
Interrupt Enable High register is set to logic 1 before the PWR_DN bit is set. The
recommended sequences for software is:
a. Set bit SESS_VLD_IEH to logic 1
b. Set bit PWR_DN to logic 1
c. Wait for interrupt from the ISP1109
d. If INT_N is asserted, read the Interrupt Latch register
e. If bit SESS_VLD_INT is logic 1, clear bit PWR_DN (Note: Software must clear
bit PWR_DN within 5 ms from the time pin INT_N is asserted. For details,
see Section 10).
Pin ISET will remain LOW when VCC is below Vth(ISET). Pin ISET can also be controlled by
software through register bits. If bit ISET_DRV_EN is set to logic 1, the status of the ISET
pin will be determined by bit ISET_STATE.
7.9 USB transceiver
7.9.1 Differential driver
The operation of the driver is described in Table 6.
Table 6: Transceiver driver operating setting
Pin
RESET_N [1] OE_N
Pin or bit
SUSPEND
Bit DAT_SE0
HIGH
LOW 0
0
HIGH
LOW 0
1
HIGH
LOW 1
X
HIGH
HIGH X
X
LOW
X
X
X
[1] Include the internal power-on-reset pulse (active HIGH).
Differential driver
output value from DAT/VP to DP and
SE0/VM to DM
output value from DAT/VP to DP and
DM, if SE0/VM is LOW; otherwise,
drive both DP and DM LOW
output value from DAT/VP to DP and
DM
high-Z
high-Z
Table 7 shows the behavior of the transmit operation in detail.
Table 7: USB functional mode: transmit operation
USB mode
Inputs
DAT/VP
SE0/VM
DAT_SE0
LOW
LOW
DAT_SE0
HIGH
LOW
DAT_SE0
LOW
HIGH
DAT_SE0
HIGH
HIGH
VP_VM
LOW
LOW
Outputs
DP
LOW
HIGH
LOW
LOW
LOW
DM
HIGH
LOW
LOW
LOW
LOW
9397 750 13355
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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