L6391N Просмотр технического описания (PDF) - STMicroelectronics
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L6391N Datasheet PDF : 24 Pages
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L6391
Electrical characteristics
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol Pin
Parameter
Test conditions
Min. Typ. Max. Unit
Logic inputs
Vil
Low level logic threshold
Vih
1, 2, 3 High level logic threshold
voltage
0.8
1.1
V
1.9
2.25
V
Vil_S
1, 3 Single input voltage
LIN and HIN connected
together and floating
0.8
V
IHINh
IHINl
HIN logic “1” input bias
current
3
HIN logic “0” input bias
current
HIN = 15 V
HIN = 0 V
110 175 260 μA
1
μA
ILINl
ILINh
ISDh
ISDl
LIN logic “0” input bias
current
1
LIN logic “1” input bias
current
SD logic “1” input bias
current
2
SD logic “0” input bias
current
LIN = 0 V
LIN = 15 V
SD = 15 V
SD = 0 V
3
6
20
μA
1
μA
10
40 100 μA
1
μA
1. VBO = Vboot - Vout.
2. RDS(on) is tested in the following way: RDS(on) = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
Symbol Pin
Table 9. Sense comparator(1) (VCC = 15 V, TJ = +25 °C)
Parameter
Test conditions
Min. Typ.
Vio
8, 9 Input offset voltage
-15
Iib
8, 9 Input bias current
VCP+ = 1 V, VCP - = 0.5 V
Vol
2
Open-drain low level output
voltage
Iod = - 3 mA VCP+ = 1 V;
VCP - = 0.5 V;
Rpull = 100 kΩ to 5 V on
td_comp
Comparator delay
SD/OD pin; VCP - = 0.5 V;
voltage step on CP+ = 0 to
90
3.3 V
SR
2 Slew rate
CL = 180 pF; Rpu = 5 kΩ
60
1. Comparator is disabled when Vcc is in UVLO condition.
Max.
15
1
0.5
130
Unit
mV
μA
V
ns
V/μs
DocID17892 Rev 2
11/24
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